The present invention generally relates to a peripheral circuit in a dynamic semiconductor memory device which reduces the time required to output data to an external device and which reduces power consumption during data reading.
A conventional peripheral circuit in a dynamic semiconductor memory device has circuits as shown, for example, in FIG. 1 and FIG. 2. As shown in FIG. 1, the peripheral circuit includes a timing generator circuit 103, a plurality of sense amplifiers 104 (only one is shown for simplicity), column address decoders 105 for their corresponding sense amplifiers 104, and transfer gates 106 for each sense amplifier 104. As shown in FIG. 2, a main amplifier 101 and a data line bias circuit 102 are also provided. Note that 4 and 5 indicate that complementary data lines D and D#in FIG. 1 and FIG. 2 are connected to the respectively labelled lines therein.
As shown in FIG. 1, the timing generator circuit 103 has an inverter 103c connected to an input terminal 103i, and first and second delay circuits 103a and 103b serially connected to the inverter 103c. An n-channel transistor 103e is connected between ground and a pull-down transistor activation signal line 109, and a p-channel transistor 103f is connected between a pull-up transistor activation signal line 110 and a power supply.
After a start signal indicating that sense amplifier operation should begin is received at the input terminal 103i, the timing generator circuit 103 generates a control signal "a" to activate a pair of pull-down transistors 104b in a specific sense amplifier 104 through an inverter 103d from the output side of the inverter 103c as shown in FIGS. 1 and 3. The control signal "a" turns the n-channel transistor 103e on and pulls the pull-down transistor activation signal line 109 down to the ground potential.
Next, a control signal "c" to activate a pair of pull-up transistors 104a is generated from the output side of the first delay circuit 103a through inverters 103g and 103h. The control signal "c" turns the p-channel transistor 103f on, and pulls the pull-up transistor activation signal line 110 up to a power supply potential.
Finally, a control signal "b" is generated from the output side of the second delay circuit 103b through inverters 103j and 103k. This control signal "b" activates a column address decoder 105 and turns the transfer gates 106 on.
The main amplifier 101 shown in FIG. 2 consists of an n-channel transistor 101a connected to ground, a pair of n-channel pull-down transistors 101b connected to the n-channel transistor 101a, a pair of p-channel pull-up transistors 101c connected between the n-channel pull-down transistors 101b and the power supply (potential Vcc), and a p-channel transistor 101d to short-circuit complementary output lines O and O#. When a control signal .phi.6 is applied, the main amplifier 101 amplifies the signals on the data lines D and D# for output to the output lines 0 and O# through the operation of the n-channel pull-down transistors 101b and the p-channel pull-up transistors 101c.
The data line bias circuit 102 shown in FIG. 2 consists of a pair of n-channel transistors 102a and another pair of n-channel transistors 102b and a p-channel transistor 102c to short-circuit the data lines D and D#. The n-channel transistor 102a and the n-channel transistor 102b are serially connected between the power supply (potential Vcc) and ground. A junction J of the transistors 102a and 102b is connected to the data line D and a junction J# of the other transistors 102a and 102b is connected to the other data line D#. The data line bias circuit 102 receives control signals .phi.3 and .phi.4 before data reading (precisely, before main amplifier 101 operation), and pre-biases the data lines D and D# to an intermediate potential Vcc/2 between the power supply potential and the ground potential.
When reading data from a memory cell, the bit lines B and B# as shown in FIG. 1 are biased to the intermediate potential Vcc/2 in advance by a pre-charge circuit not shown in the figures. The data lines D and D# are also biased to the intermediate potential Vcc/2 by the data line bias circuit 102 shown in FIG. 2. The timing generator circuit 103 shown in FIG. 1 then generates the control signal "a" and then the control signal "c", causing the pull-down transistor activation signal line 109 to be grounded and the pull-up transistor activation signal line 110 to be pulled up to the power supply potential. Thus, a weak potential difference transferred from the memory cell over the bit lines B and B# is amplified and latched by the sense amplifier 104. The timing generator circuit 103 then generates the control signal "b", and the transfer gates 106 are made continuous to the data lines D and D# by the column address decoder 105. As a result, the potential difference latched by the sense amplifier 104 is sent from the bit lines B and B# to the data lines D and D#. The main amplifier 101 shown in FIG. 2 then amplifies the potential difference on the data lines D and D#, and outputs the result to the output lines 0 and 0#.
The conventional peripheral circuit as described hereinabove, however, during data reading, drives the pull-down transistors 104b in the sense amplifier 104 first to pull down the potential of one of the bit lines B and B#, and then drives the pull-up transistors 104a to pull up the potential of the other of the bit lines B and B# before sending the data to the data lines D and D#. As a result, during the period from the start of sense amplifier operation until the start of data transfer to the data lines D and D#, operating time is required to pull down the potential of the bit lines B or B# (corresponding to the output timing difference between the control signals "a" and "c") and to pull up the potential of the bit line D# or D (corresponding to the output timing difference between the control signals "c" and "b"). As a result, a prolonged time is thus required for output of data over the output lines O and O# through the main amplifier 101.
In addition, when the data lines D and D# are pre-biased to the intermediate potential Vcc/2 before main amplifier operation begins, a DC current flows from the power supply Vcc to ground through the n-channel transistors 102b and 102a in the data line bias circuit 102. As a result, power consumption is greatly increased.